You are ready to run C Simulation on the project, but first you can configure the simulation by editing the hls_config.cfg file.
In the open vitis-comp.json for the dct component click the hls_config.cfg link to open the Configuration Editor. On the left is a list of categories for configuring the HLS component, and on the right are the various configuration options.
You can see the General settings of the dct component reflect the part, clock and flow_target settings you specified when creating the HLS component. Scroll down and you can see the C Synthesis sources and Testbench sources you added as well.
On the left, select the C Simulation category.
Review the various simulation settings.
Look at the Flow Navigator with the dct component active. It displays the C Simulation step, C Synthesis, C/RTL Co-simulation, and Implementation as the primary steps of the HLS component workflow.
Click Run under C SIMULATION.
The Output window is displayed in the console area, and the dct::c_simulation transcript is displayed. You can review the transcript as simulation occurs.
After simulation completes the Reports beneath C Simulation show a summary you can view. It merely shows the command used to launch C simulation and the timestamp of the run. In the Vitis unified IDE the simulation uses the following command line:
vitis-run --mode hls --csim --work_dir dct \
--config <tutorial_path>/Getting_Started/Vitis_HLS/reference-files/workDCT/dct/hls_config.cfg