In this step, you are going to create an HLS component by using the files provided in the 1Dfix_impulse L1 examples of the Vitis dsp library. The source files and script file are all located under this folder.
Launch Vitis Unified IDE
vitis
Select File > New Component > HLS to create a new HLS component.
This opens the Name and Location page of the Create HLS Component wizard
Enter the Component name:
implTestEnter the Component location: Point to the folder serves as workspace. e.g. myProject
Click Next to move forward
This opens the Configuration File page
Select the Empty File radio button
Leave the New configuration file name as the default:
hls_configClick Next to move forward
This opens the Add Source Files page
Under Design Files select the Add Files command icon,
Browse to the
<installdir>/Vitis_Libraries/dsp/L1/examples/1Dfix_impulse/srcfolder, select thetop_module.cppfile, and click Open to add the file and close the dialog.In the CFLAGS entry field next to the
top_module.cppfile, paste the following text to provide an include path:-I./Select Browse next to Top Function
Select the
fft_top(int * int *)top module, and select OK to close the dialog boxUnder Test Bench Files select the Add Files command icon
Browse to
examples/1Dfix_impulse/srcfolder, select themain.cppfile, and click Open to add the file and close the dialog.In the CFLAGS entry field next to the
main.cppfile, paste the following text to provide an include path:-I./Click Next to move forward.
This opens the Hardware page
Click Next to accept the default part and move forward.
This opens the Settings page.
Click Next to accept all defaults and move forward.
This opens the Summary page.
Review the page contents and click Finish to create the HLS component as defined.
The HLS component is created in the Vitis unified IDE and opened in the Flow Navigator. Now we need to set the relative_roots for the include path.
Open the
hls_config.cfgconfiguration file by selecting it under the Settings heading in the Vitis Components Explorer view, or by selecting it from the openvitis-comp.jsonfile for the HLS component.From All Settings > General, Click Add item under hls.relative_roots, input
<installdir>/Vitis_Libraries/dsp/L1/include/hw/vitis_fft/fixed
You can browse into the Settings, view and open the top_module.cpp file by selecting the source file in the Vitis Explorer view. The top_module.cpp calls the FFT library and the parameters are defined in the data_path.hpp file. For detailed instructions on using the FFT library, refer to the Vitis DSP Library.
In Flow Navigator select Run under the C Simulation
Select Run under the C Synthesis
Select Run under the C/RTL Co-simulation
After C/RTL Co-Simulation, the following results are returned.
...
===============================================================
--Input Impulse:
(1,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
(0,0)
===============================================================
===============================================================
--Output Step fuction:
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
(1,0)
===============================================================
INFO: [COSIM 212-1000] *** C/RTL co-simulation finished: PASS ***
...
The testbench uses a single pulse signal as input to the FFT and the output should be a step signal. And these can be verified by looking at the values printed out to the screen.
View the Waveform during C/RTL Co-Simulation (optional)
Open the hls_config.cfg configuration file
Scrool down to the C/RTL Cosimulation section of the Config File editor
Under hls.cosim.trace_level select all
Enable the hls.cosim.wave_debug option
In the Flow Navigator select Run under the C/RTL Co-simulation heading
In this way, you get the simulation waveform, such as the following example for a single SSR stream port:
Use the interface signals behavior in co-simulation waveform as a reference for the Vivado simulation testbench.
Export the HLS Component as a Vivado IP
Now that you have verified that the library IP is working properly you can export your design to a Vivado™ IP.
Click Run under the Package heading in the Flow Navigator
By default the IP is exported to the myProject/implTest/fft_top folder to the fft_top.zip file. This file contais the zipped contents of the Vivado IP, and can be added to your IP Catalog for use in the Vivado Design Suite RTL designs and IP Integrator designs.