Running High-Level Synthesis and Analyzing Results - 2025.1 English - XD098

Vitis Tutorials: Getting Started (XD098)

Document ID: XD098
Release Date: 2025-06-17
Version: 2025.1 English

Getting_Started
Vitis Introduction and Getting Started
Understanding the Vitis Tool Flow
What is Vitis?
How to get started with Vitis?
Vitis Component Level Tools and Flow
AI Engine Graph Creation Overview
Vitis HLS Kernel Creation Overview
System Level Tools and Flow
Vitis Platform Creation Overview
Embedded Application Creation Overview
Vitis Linker
Vitis Packager
Getting Started with Designing using the Vitis Tool
Prepare AI Engine kernel
1. Basics of Matrix Multiplication
2. AI Engine Kernel Overview
3. AI Engine Standalone Compilation:
4. AI Engine Standalone Simulation:
AI Engine commands and its output:
Prepare HLS kernels
1. Compile of MM2S HLS kernel
2. Compile of S2MM HLS kernel
Create a host application using AMD VCK190 platform
Compilation of Host Code:
Use Vitis Linker and Packager to build the design
Vitis Linker
1. Vitis Linker Configuration File
2. Running the Vitis Linker
Before the Linker Run (Extensible XSA)
After the Linker Run (Fixed XSA)
Vitis Linker command and its output
Vitis Packager
1. Vitis Packager Configuration File
2. Running the Vitis Packager
Vitis Packager command and its output
Running the Hardware Emulation
Steps to run the Hardware Emulation
Running the design on a VCK190 Evaluation Board
Steps to run the design on Hardware
1. Connect the VCK190 board and set the SD boot mode
2. Flash the SD Card
3. Running the design and application on the VCK190
Important Terms
What is XSA?
What is a Kernel?
What is XRT/AMD Runtime Library?
Vitis HLS
Using the New Vitis Unified IDE
Conclusion
Running High-Level Synthesis and Analyzing Results
Run the C Simulation
Run C Synthesis
Analyze the Results
Next Step
Using Optimization Techniques
Loop Pipeline
Pipeline Directive
Assign Dual-Port RAMs with BIND_STORAGE
Using Array_Partition
Next Step
Reviewing the DATAFLOW Optimization
Clone Component for Design Exploration
Adding the Dataflow Directive
Run C/RTL Co-Simulation
View the Dataflow Graph
Running Implementation to Improve Timing and Resource Estimates
Export the Vitis Kernel
Summary
Vitis Libraries
Before You Begin
Setup Environment
Get Vitis Libraries
Create and run an HLS Component
Use the Exported IP in the Vivado Design Suite
Summary
Reference
Vitis Platform
Step 1: Create Vivado Design and Generate XSA
Step 2: Create Vitis Platform
Step 3: Validate this Vitis PLatform
Run the Application on Hardware
Fast Track

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