Migrating an I/O Planning Project to an RTL Project - 2022.1 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)
Document ID
UG899
Release Date
2022-05-04
Version
2022.1 English
After the I/O ports are defined and placed onto the package pins, you can migrate the I/O planning project to an RTL project. The port definitions are used to create a top module for the RTL design in either Verilog or VHDL, as specified. Differential pair buffers are added to the top module, and bus definitions are also included in the RTL. The project properties are changed to reflect the RTL project type.
Important: After migration, the RTL project cannot be converted back into an I/O planning project.

To convert the project:

  1. Select File > Migrate to RTL.

    Note: Alternatively, you can select Migrate to RTL from the Flow Navigator.

  2. In the Migrate to RTL dialog box (see the following figure), set the following options, and click OK.
    Top RTL file
    Specify the Verilog (.v extension) or VHDL (.vhd extension) file to create for the top module of the design. The HDL file will include the module definition with port definitions, direction, and width for bus pins.
    Netlist format
    Specify Verilog or VHDL format for the top module.
    Write diff buffers
    Write the diff pair buffers as part of the top module definition. This preserves any differential pairs defined in the I/O planning project.


    After the I/O planning project is converted to an RTL project, you can begin adding sources to the project and working on your design. For more information, see section "Working with source files" in the Vivado Design Suite User Guide: System-Level Design Entry (UG895).