You can view the interfaces that are connected from an IP to the top-level ports
of your design. For these IP interfaces, the Vivado
tools automatically infer a pin planning interface that groups the related top-level I/O
ports. This provides a symbolic way of referring to the interface in the context of the
top-level design. For example, in the following figure, the led_8bits_tri_o bus is a general purpose I/O (GPIO) interface that is
grouped under the GPIO_9847 pin planning interface.
You can view the board part pins associated with the I/O ports from the Board Part Pin
column in the I/O Ports window. In the following figure, the ports associated with
pin-planning interface GPIO_9847 are constrained to board part pins
led_8bits_tri_o[7:0].
