PHY Implementation - 2022.1 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

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2022.1 English

UltraScale architecture Memory IP defines a memory controller using a pre-engineered controller and PHY for interfacing user designs and AMBA specification AXI4 slave interfaces to DDR3, DDR4, QDRII+, QRDRIV, and RLDRAM3 SRAM devices.

The Memory IP is structured so that only the physical layer (PHY) interconnect in the Xilinx® device needs to be updated when pinouts change. Because the PHY implementation depends on the I/O assignments, it must occur after the I/Os are placed and validated. To enable memory I/O planning after synthesis, the implementation of the PHY now happens as a part of implementation during the opt_design command.