I/O Planning for Versal ACAP - 2022.1 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)
Document ID
UG899
Release Date
2022-05-04
Version
2022.1 English

The two primary types of I/O in Versal ACAPs are high-performance XP I/O (XPIO) and high density HD I/O (HDIO). The XPIO includes dedicated logic to support high-speed interfaces with voltage ranges between 1.0V and 1.5V. HDIO and XPIO banks do not have overlapping voltages or I/O standards. The HDIO supports interfaces with voltages ranging from 1.8V to 3.3V. The HDIO provides logic for both single data rate (SDR) and double data rate (DDR) interfaces at reduced clocking speeds. See Versal ACAP SelectIO Resources Architecture Manual (AM010) for architecture information and Advanced I/O Wizard LogiCORE IP Product Guide (PG320) for detailed information on Advanced IO Wizard / Advanced IO Planner.

All Versal devices have configurable SelectIO interface drivers and receivers, supporting a wide variety of standard interfaces. The robust feature set includes programmable control of output strength and slew rate, on-chip termination, and an internally generate a reference voltage (INTERNAL_VREF). Each Versal device contain XPIO banks that contain 54 SelectIO pins and can implement both single-ended and differential I/O standards. XPIO banks support the highest speed interfaces powered at or below 1.5V. Some Versal devices contain HDIO banks that can interface with voltage levels between 1.8V and 3.3V. The HDIO banks contain 22 SelectIO pins that can implement both single-ended I/O standards and differential I/O standards. Every SelectIO IOB resource contains input, output, and tristate drivers. The SelectIO pins can be configured to various I/O standards, both single-ended and differential.
  • Single-ended I/O standards are, for example, LVCMOS, LVTTL, HSTL, SSTL, HSUL, LVSTL, and POD.
  • Pseudo-differential standards are, for example, differential HSTL, POD, HSUL, LVSTL, and SSTL.
  • LVDS compatible.