Interface Synthesis Requirements - 2022.1 English

To use the C/RTL co-simulation feature to verify the RTL design, at least one of the following conditions must be true:

• Top-level function must be synthesized using an ap_ctrl_chain or ap_ctrl_hs block-level protocol
• Design must be purely combinational
• Top-level function must have an initiation interval of 1
• Interfaces must be all arrays that are streaming and implemented with axis or ap_hs interface modes
  Note: The hls::stream variables are automatically implemented as ap_fifo interfaces.

If at least one of these conditions is not met, C/RTL co-simulation halts with the following message:

@E [SIM-345] Cosim only supports the following 'ap_ctrl_none' designs: (1) 
combinational designs; (2) pipelined design with task interval of 1; (3) designs with 
array streaming or hls_stream ports.
@E [SIM-4] *** C/RTL co-simulation finished: FAIL ***

If any top-level function argument is specified as an AXI4-Lite interface, the function return must also be specified as an AXI4-Lite interface.