In the following code, an array is initialized with a set of values. Each time the
function is executed, array coeff is assigned these
values. After synthesis, each time the design executes the RAM that implements coeff is loaded with these values. For a single-port RAM
this would take eight clock cycles. For an array of 1024, it would of course take 1024
clock cycles, during which time no operations depending on coeff could occur.
int coeff[8] = {-2, 8, -4, 10, 14, 10, -4, 8, -2};
The following code uses the static qualifier to
define array coeff. The array
is initialized with the specified values at start of execution.
Each time the function is executed, array coeff remembers its values
from the previous execution. A static array behaves in C/C++
code as a memory does in RTL.
static int coeff[8] = {-2, 8, -4, 10, 14, 10, -4, 8, -2};
In addition, if the variable has the static
qualifier, Vitis HLS
initializes the variable in the RTL design and in the FPGA
bitstream. This removes the need for multiple clock cycles to
initialize the memory and ensures that initializing large
memories is not an operational overhead.
The RTL configuration command can specify if static variables return to their initial state after a reset is applied (not the default). If a memory is to be returned to its initial state after a reset operation, this incurs an operational overhead and requires multiple cycles to reset the values. Each value must be written into each memory address.