set_directive_interface - 2022.1 English

Description

Specifies how RTL ports are created from the function description during interface synthesis. For more information, see Defining Interfaces. The ports in the RTL implementation are derived from:

• Any function-level protocol that is specified.
• Function arguments and return.

Function-level handshakes:

• Control when the function starts operation.
• Indicate when function operation:
  • Ends
  • Is idle
  • Is ready for new inputs

The implementation of a function-level protocol:

• Is controlled by modes ap_ctrl_chain, ap_ctrl_hs, or ap_ctrl_none.
• Requires only the top-level function name.

Each function argument can be specified to have its own I/O protocol (such as valid handshake or acknowledge handshake).

Syntax

set_directive_interface [OPTIONS] <location> <port>

• <location> is the location (in the format function[/label]) where the function interface or registered output is to be specified.
• <port> is the parameter (function argument) for which the interface has to be synthesized. The port name is not required when block control modes are specified: ap_ctrl_chain, ap_ctrl_hs, or ap_ctrl_none.

Options

-bundle <string>

By default, the HLS tool groups or bundles function arguments with compatible options into interface ports in the RTL code. All AXI4-Lite (s_axilite) interfaces are bundled into a single AXI4-Lite port whenever possible. Similarly, all function arguments specified as an AXI4 (m_axi) interface are bundled into a single AXI4 port by default.

All interface ports with compatible options, such as mode, offset, and bundle, are grouped into a single interface port. The port name is derived automatically from a combination of the mode and bundle, or is named as specified by -name.

Important: When specifying the bundle name you should use all lower-case characters.

-clock <string>

By default, the AXI4-Lite interface clock is the same clock as the system clock. This option is used to set specify a separate clock for an AXI4-Lite interface. If the -bundle option is used to group multiple top-level function arguments into a single AXI4-Lite interface, the clock option need only be specified on one of bundle members.

-depth <int>

Specifies the maximum number of samples for the test bench to process. This setting indicates the maximum size of the FIFO needed in the verification adapter that the HLS tool creates for RTL co-simulation.

Tip: While depth is usually an option, it is required for m_axi interfaces and determines the amount of resources allocated for the adapter as explained in AXI4 Master Interface.

-latency <value>

This option can be used on ap_memory and M_AXI interfaces.

• In an ap_memory interface, the interface option specifies the read latency of the RAM resource driving the interface. By default, a read operation of 1 clock cycle is used. This option allows an external RAM with more than 1 clock cycle of read latency to be modeled.
• In an M_AXI interface, this option specifies the expected latency of the AXI4 interface, allowing the design to initiate a bus request <value> number of cycles (latency) before the read or write is expected. If this figure it too low, the design will be ready too soon and may stall waiting for the bus. If this figure is too high, bus access may be idle waiting on the design to start the access.

-max_read_burst_length <int>

For use with the M_AXI interface, this option specifies the maximum number of data values read during a burst transfer.

-max_widen_bitwidth <int>

Specifies the maximum bit width available for the interface when automatically widening the interface. This overrides the global value specified by the config_interface -m_axi_max_bitwidth command.

-max_write_burst_length <int>

For use with the M_AXI interface, this option specifies the maximum number of data values written during a burst transfer.

-mode (ap_none|ap_vld|ap_ack|ap_hs|ap_ovld|ap_fifo|ap_memory|bram|axis|s_axilite|m_axi|ap_ctrl_none|ap_ctrl_hs|ap_ctrl_chain|ap_stable)

Following is a summary of how Vitis HLS implements the -mode options.

• ap_none: No protocol. The interface is a data port.
• ap_vld: Implements the data port with an associated valid port to indicate when the data is valid for reading or writing.
• ap_ack: Implements the data port with an associated acknowledge port to acknowledge that the data was read or written.
• ap_hs: Implements the data port with associated valid and acknowledge ports to provide a two-way handshake to indicate when the data is valid for reading and writing and to acknowledge that the data was read or written.
• ap_ovld: Implements the output data port with an associated valid port to indicate when the data is valid for reading or writing.
  Note: Vitis HLS implements the input argument or the input half of any read/write arguments with mode ap_none.
• ap_fifo: Implements the port with a standard FIFO interface using data input and output ports with associated active-Low FIFO empty and full ports.
  Note: You can only use this interface on read arguments or write arguments. The ap_fifo mode does not support bidirectional read/write arguments.
• ap_memory: Implements array arguments as a standard RAM interface. If you use the RTL design in Vivado IP integrator, the memory interface appears as discrete ports.
• bram: Implements array arguments as a standard RAM interface. If you use the RTL design in Vitis IP integrator, the memory interface appears as a single port.
• axis: Implements all ports as an AXI4-Stream interface.
• s_axilite: Implements all ports as an AXI4-Lite interface. Vitis HLS produces an associated set of C driver files during the Export RTL process.
• m_axi: Implements all ports as an AXI4 interface. You can use the config_interface command to specify either 32-bit (default) or 64-bit address ports and to control any address offset.
• ap_ctrl_none: No block-level I/O protocol.
  Note: Using the ap_ctrl_none mode might prevent the design from being verified using the C/C++/RTL co-simulation feature.
• ap_ctrl_hs: Implements a set of block-level control ports to start the design operation and to indicate when the design is idle, done, and ready for new input data.
  Note: The ap_ctrl_hs mode is the default block-level I/O protocol.
• ap_ctrl_chain: Implements a set of block-level control ports to start the design operation, continue operation, and indicate when the design is idle, done, and ready for new input data.
• ap_stable: No protocol. The interface is a data port. Vitis HLS assumes the data port is always stable after reset, which allows internal optimizations to remove unnecessary registers.

-name <string>

Specifies a name for the port which will be used in the generated RTL.

-num_read_outstanding <int>

For use with the M_AXI interface, this option specifies how many read requests can be made to the AXI4 bus, without a response, before the design stalls. This implies internal storage in the design, and a FIFO of size:

num_read_outstanding*max_read_burst_length*word_size

-num_write_outstanding <int>

For use with the M_AXI interface, this option specifies how many write requests can be made to the AXI4 bus, without a response, before the design stalls. This implies internal storage in the design, and a FIFO of size:

num_read_outstanding*max_read_burst_length*word_size

-offset <string>

Controls the address offset in AXI4-Lite (s_axilite) and AXI4 memory mapped (m_axi) interfaces for the specified port.

• In an s_axilite interface, <string> specifies the address in the register map.
• In an m_axi interface this option overrides the global option specified by the config_interface -m_axi_offset option, and <string> is specified as:
  • off: Do not generate an offset port.
  • direct: Generate a scalar input offset port.
  • slave: Generate an offset port and automatically map it to an AXI4-Lite slave interface. This is the default offset.

-register

Registers the signal and any associated protocol signals and instructs the signals to persist until at least the last cycle of the function execution. This option applies to the following scalar interfaces for the top-level function:

• s_axilite
• ap_fifo
• ap_none
• ap_stable
• ap_hs
• ap_ack
• ap_vld
• ap_ovld

-register_mode (both|forward|reverse|off)

This option applies to AXI4-Stream interfaces, and specifies if registers are placed on the forward path (TDATA and TVALID), the reverse path (TREADY), on both paths (TDATA, TVALID, and TREADY), or if none of the ports signals are to be registered (off). The default is both. AXI4-Stream side-channel signals are considered to be data signals and are registered whenever the TDATA is registered.

-storage_impl=<impl>

For use with s_axilite only. This options defines a storage implementation to assign to the interface.

Supported implementation values include auto, bram, and uram. The default is auto.

Tip: uram is a synchronous memory with only a single clock for two ports. Therefore uram cannot be specified for an s_axilite adapter with a second clock.

-storage_type=<type>

For use with ap_memory and bram interfaces only. This options defines a storage type (for example, RAM_T2P) to assign to the variable.

Supported types include: ram_1p, ram_1wnr, ram_2p, ram_s2p, ram_t2p, rom_1p, rom_2p, and rom_np.

Tip: This can also be specified using the BIND_STORAGE pragma or directive for the variable for objects that are not defined on the interface.

Examples

Turns off function-level handshakes for function func.

set_directive_interface -mode ap_ctrl_none func

Argument InData in function func is specified to have a ap_vld interface and the input should be registered.

set_directive_interface -mode ap_vld -register func InData

See Also

• pragma HLS interface
• set_directive_bind_storage