Target Processor - 2022.1 English

Versal ACAP System Integration and Validation Methodology Guide (UG1388)

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2022.1 English

The target processor for the application can be an Arm® Cortex®-A72 processor, Cortex-R5F processor, MicroBlaze™ processor in PL, or AI Engine core processor. Depending on the processor type, the debugger can connect to one of the processor targets and perform single-stepping, breakpoint insertion to debug specific portion of the code. If the target processor is Cortex-A72 or Cortex-R5F, it is possible to connect to the Arm CoreSight™ interface using HSDP or JTAG. Vitis debugger or third-party debuggers (for example, Lauterbach) can connect to the CoreSight interface and perform single-stepping, breakpoint insertion, instruction disassembly, core register status, etc.

For an AI Engine processor, Vitis debugger can connect to the AI Engine debug interface and perform single-stepping, breakpoint insertion, and view program/data memory. Vitis debugger can connect to the target processor using the XSCT interface. The XSCT interface provides a full set of debug commands to read internal registers and memory of a processor. For example, if software code hangs at a specific instruction, you can read the PC address and check the last instruction it executed. For more information about XSCT commands, see the Xilinx Software Command-Line Tool in the Vitis Embedded Software Development Flow Documentation (UG1400).