ILA Core Designs with High-Speed Clocks - 2022.1 English

Versal ACAP System Integration and Validation Methodology Guide (UG1388)
Document ID
UG1388
Release Date
2022-05-25
Version
2022.1 English

For designs with high-speed clocks, consider the following:

  • Limit the number and width of signals being debugged.
  • Pipeline the input probes to the AXIS-ILA by setting the number of input pipeline stages. This setting can be found in the Advanced tab of the AXIS-ILA GUI or set with the C_INPUT_PIPE_STAGES property when using Tcl insertion.