AXI4 Debug Hub Connectivity - 2022.1 English

Versal ACAP System Integration and Validation Methodology Guide (UG1388)

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2022.1 English

To use the Vivado® debug cores, the design must contain an AXI4 debug hub. The AXI4 debug hub connects an AXI-MM interface of the CIPS with the AXI4-Stream interface. The interface connects to Vivado debug cores, which includes the following types of cores:

  • AXI4-Stream Integrated Logic Analyzer (AXIS-ILA)
  • AXI4-Stream Virtual Input/Output (AXIS-VIO)
  • PCI Express® Link Debugger

If the design contains any Vivado debug cores and the CIPS has one or more PL resets enabled, the AXI4 debug hub is automatically inserted by Vivado during opt_design and connected to the CIPS using a NoC. It is possible to instantiate the AXI4 debug hub and connect it to the CIPS manually, but the automatic insertion will not take place.

Three different scenarios can determine if AXI4 debug hub auto-insertion will occur during opt_design:

Table 1. AXI4 Debug Hub Auto-Insertion
Synthesized Netlist Contents AXI4 Debug Hub Insertion Action
CIPS with one or more PL Reset Enabled. No AXI4 debug hubs. An AXI4 debug hub will be inserted during opt_design and connected to the CIPS using a NoC instance.
CIPS with one pre-existing AXI4 debug hub Any debug cores in the design that are not found to be manually connected to an AXI4 debug hub will be connected to the preexisting debug hub during opt_design.
CIPS with multiple AXI4 debug hubs

Automatic stitching will not occur without taking one of the two actions:

  • The AXI4-Stream interfaces on the debug cores are manually connected to the desired AXI4 debug hub.
  • The connectivity between each debug core and associated AXI4 debug hub is specified using the

    connect_debug_core constraint.