Checking for Valid Constraints - 2022.1 English

Versal ACAP System Integration and Validation Methodology Guide (UG1388)

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2022.1 English

Review the Check Timing section of the Timing Summary report to quickly assess the timing constraints coverage, including the following:

  • All active clock pins are reached by a clock definition.
  • All active path endpoints have requirement with respect to a defined clock (setup/hold/recovery/removal).
  • All active input ports have an input delay constraint.
  • All active output ports have an output delay constraint.
  • Timing exceptions are correctly specified.
    Excessive use of wildcards in constraints can cause the actual constraints to be different from what you intended. Use the report_exceptions command to identify timing exception conflicts and to review the netlist objects, timing clocks, and timing paths covered by each exception.

In addition to check_timing, the Methodology report (TIMING and XDC checks) flags timing constraints that can lead to inaccurate timing analysis and possible hardware malfunction. You must carefully review and address all reported issues.

Note: When baselining the design, you must use all Xilinx IP constraints. Do not specify user I/O constraints, and ignore the violations generated by check_timing and report_methodology due to missing user I/O constraints. For more information on baselining the design, see Baselining the Design.