Using the Vivado ILA Core to Debug JTAG-AXI Transactions - 2021.2 English

Vivado Design Suite Tutorial: Programming and Debugging

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2021.2 English

This lab illustrates how to insert an ILA core into the JTAG to AXI Master IP core example design, using the ILA's advanced trigger and capture capabilities.

What is the JTAG to AXI Master IP core?

The LogiCORE™ LogiCORE IP JTAG-AXI core is a customizable core that can generate AXI transactions and drive AXI signals internal to the FPGA at run-time. This supports all memory-mapped AXI interfaces (except AXI4-Stream) and Lite protocol and can be selected using a parameter. The width of the AXI data bus is customizable. This IP can drive any AXI4-Lite or Memory-Mapped Slave directly. It can also be connected as master to the interconnect. Run-time interaction with this core requires the use of the Vivado® logic analyzer feature.

Key Features

  • AXI4 master interface
  • Option to select AXI4 and AXI4-Lite interfaces
  • User controllable AXI read and write enable
  • User Selectable AXI data width: 32 and 64
  • Vivado Integrated Logic Analyzer Tcl Console interface to interact with hardware

Additional Documentation

JTAG to AXI Master LogiCORE IP Product Guide (PG174) contains additional information