IBERT PS-GTR Flow - 2021.2 English

Vivado Design Suite Tutorial: Programming and Debugging

Document ID
Release Date
2021.2 English

The IBERT PS-GTR Bring-up and subsequent EyeScan involves three different components:

  1. Generating Zynq UltraScale+ MPSoC PS Xilinx® Support Archive (XSA) file from the Vivado® tool after configuring the PS-GTR.
  2. Using the Vitis™ Xilinx Software Command-line Tool (XSCT) flow to generate a FSBL file using the XSA file.
  3. Using the FSBL file with Vivado Serial I/O Analyzer to bring up IBERT PS-GTR.

Tools Required

  • Vivado
  • Vitis
  • XSCT (Part of the Vitis tool)

Board/Part/Components Required

  • ZCU102 Rev 1.0 board
  • XCZU9EG-FFVB1156 production device
  • PCIe®
    • A PCIe card which has at least x4 lanes
    • PCI Express 4x Male to PCIe 16x Female Riser Cable if PCIe card is larger than x4
  • SATA
    • SanDisk 128 GB SATA SSD Drive
    • SATA connector cable
    • 4 Pin Molex to SATA Power Cable Adapter
  • USB
    • SanDisk Ultra 32 GB USB 3.0 Flash Drive
    • USB 3.0 Type A Female to Micro Male Adapter

Required Files

  • FSBL executable and linkable format file (ELF File) (Created using the following instructions) which configures the PS-GTR
  • Configuration Bitstream File (Optional file that may be needed to custom configure the FPGA depending on the board setup)
  • Tcl script to generate the FSBL and modify C-source for USB Support (when available)


  1. FSBL should always target Cortex®-A53 processor as R5 (psu_cortexr5_0) is exclusively used by IBERT PS-GTR.
  2. Physical devices such as SATA drive, PCIe card, etc. are needed for validation.