Step 1: Create a Synplify Pro Project - 2021.2 English - UG936

Vivado Design Suite Tutorial: Programming and Debugging
Document ID
UG936
Release Date
2021-11-10
Version
2021.2 English
  1. Launch Synplify Pro and select File > New.
  2. Set File Type to Project File (Project) as highlighted in the following figure.
  3. In the New File Name box, enter synplify_1.
  4. Click OK.

  5. If you get a dialog box asking you to create a non-existing directory, click OK.

  6. In the left panel of the Synplify Pro window, click Add File as shown in the following figure.

  7. In the Add Files to Project dialog box, change the Files of Type to HDL File. Navigate to C:\Vivado_Debug\src\lab4, which shows all the VHDL source files needed for this lab. Select the following three files by pressing the Ctrl key and clicking on them.
    • debounce.vhd
    • fsm.vhd
    • sinegen_demo.vhd
  8. Click Add.

  9. In the same dialog box set Files of type to Constraints Files. This shows the synplify_1.sdc file. Select the file and click Add as shown in the following figure.

  10. In the same dialog box, set Files of type to FPGA Constraint Files. This shows the synplify_1.fdc file. Select the file and click Add as shown in the following figure. Click OK.

  11. Now, you need to set the implementation options.
  12. Click Implementation Options in the Synplify Pro window as shown in the following figure.

  13. This brings up the Implementation Options dialog box as shown in the following figure. In the Device tab, set Technology to Xilinx Kintex7, Part to XC7K325T, Package to FFG900 and Speed to -2. Leave all the other options at their default values. Click OK.

  14. You need to preserve the net names that you want to debug by putting attributes in the HDL files. These attributes are already placed in the sinegen_demo.vhd, file of this tutorial. Open the sinegen_demo.vhd file and inspect the lines shown.

  15. You also can specify the MARK_DEBUG attributes in the source HDL files to mark the signals for debug, as shown in the code snippet from singen_demo.vhd file.

  16. The synplify_1.sdc file contains various kinds of constraints such as pin location, I/O standard, and clock definition. The synplify_1.fdc file contains directives for the compiler. Here is where the nets of interest to us that are marked for debug are located. The attribute and the nets selected for debug are shown in the following figure.

    In the above constraints, sinegen has been defined as a black box by using the syn_black_box attribute. Second, the syn_no_prune attribute has been used so that the I/Os of this block are not optimized away. Finally, two nets, sine[20:0] and sel[1:0], have been assigned the MARK_DEBUG attribute such that these two nets should show up in the synthesized design in Vivado® IDE for further debugging. For further information on these attributes, please refer to the Synplify Pro User Manual and Synplify Pro Reference Manual.