Step 8: Incorporating SAIF Data into Power Analysis - 2021.1 English

Vivado Design Suite Tutorial: Power Analysis and Optimization (UG997)

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2021.1 English

The SAIF output file requested in the simulation run is generated in the project directory. This SAIF file is used to further guide the power analysis algorithm.

  1. Ensure the SAIF file requested is generated. Check to see that the SAIF file requested in the simulation settings prior to running simulation appears in this directory:

    <project_directory>/power_tutorial1/power_tutorial1.sim/sim_1/synth/ func/power_tutorial_func.saif

  2. In the Flow Navigator window, click on Open Synthesized Design to expand options.
  3. From the Synthesized Design options, select Report Power.
  4. In the Report Power dialog box, set the Results name to power_3.
  5. In the Output tab of Report Power dialog box, make the following changes:
    • Set the Output text File to power_3.pwr
    • Set the Output XPE File to power_3.xpe
  6. In the Environment tab of Report Power dialog box, make sure that the Process is set to maximum.
  7. In the Switching tab of Report Power dialog box, specify the SAIF file location.

  8. Click OK in the Report Power dialog box.

    The report_power command runs, and the Power Report power_3 is generated in the Power window.

    Note: The SAIF annotation results are displayed in the Tcl Console. Make sure that all the design nets are matched with simulation nets, to achieve better accuracy by including Simulation data. For 7 series devices, the number of design nets and simulation nets may vary due to various reasons. The most common reason is that their hierarchical separators are different. Sometimes, the simulation nets may be lower down in the hierarchy level. However, they should match 100%.

    Example: INFO: [Power 33-26] Design nets matched = 1894 of 1894

  9. Go to the I/O view in the Power window. Note that all the I/O port activity data has been set from simulation data we specified. The data is color coded to indicate activity rates read from the simulation output file.

  10. Note the difference in total power numbers (Total On-Chip Power in the Summary view) between a pure vectorless run in the power_1 results versus with the post synthesis functional simulation data in the power_3 results. Also note that the dut/dut_reset signal rates are overwritten by simulation SAIF data.