Conclusion - 2021.1 English

Vivado Design Suite Tutorial: Power Analysis and Optimization (UG997)

Document ID
UG997
Release Date
2021-06-30
Version
2021.1 English

In this tutorial, we have accomplished the following:

  • Used the Report Power dialog box to verify and set device, thermal, and environmental conditions that contribute to power estimation.
  • Synthesized the design and estimated the power after synthesis.
  • Set switching activities on an I/O port and reran Report Power.
  • Ran functional simulation using the Vivado simulator and generated a SAIF file that is input to Report Power for a more accurate power analysis.
  • Implemented the design, ran post-implementation timing simulation using the Vivado simulator, and generated a SAIF file that is input to report power for a more accurate power analysis.
  • Ran Questa Advanced Simulator post-implementation timing simulation and generated a SAIF file that is input to report power for a more accurate power analysis.
  • Performed power measurement on the design implemented in a KC705 and KCU105 Evaluation Boards. Compared the hardware power numbers with the numbers generated by Vivado Report Power.
  • Learned how to achieve power optimization as part of an implementation run.
  • Examined the power optimization report and selectively turned off power optimizations on a cell in the design.
  • Examined the power saving of UltraScale block RAMs in cascaded mode when compared to block RAMs in Non-cascaded mode.