Step 1: Creating a New Project - 2021.1 English

Vivado Design Suite Tutorial: Power Analysis and Optimization (UG997)
Document ID
UG997
Release Date
2021-06-30
Version
2021.1 English
To create a project, use the New Project wizard to name the project, to add RTL source files and constraints, and to specify the target device.
Note: Throughout this tutorial, Xilinx® 7 series example design is used to explain the process of configuring, implementing, estimating the power through different stages, and using simulation data to enhance the accuracy of the power analysis. For UltraScale™ device design, most of the steps are similar to 7 series. Additional information, wherever necessary, is provided for UltraScale devices.

On Linux, do the following.

  1. Go to the directory where the lab materials are stored:

    cd <Extract_Dir>/7_series (for 7 series devices) or

    cd <Extract_Dir>/UltraScale (for UltraScale devices)

  2. Launch the Vivado IDE: vivado

    On Windows, do the following.

  3. Launch the Vivado IDE by selecting Start > All Programs > Xilinx Design Tools > Vivado 2021.x > Vivado 2021.x (x denotes the latest version of Vivado 2021 IDE).

    As an alternative, click the Vivado 2021.x Desktop icon to start the Vivado IDE.

    The Vivado IDE Getting Started page contains links to open or create projects and to view documentation.

  4. In the Getting Started page, click Create New Project to start the New Project wizard.
  5. Click Next to continue to the next screen.

  6. In the Project Name page, name the new project power_tutorial1 and enter the project location (C:\Vivado_Power_Tutorial). Make sure to check the Create project subdirectory option and click Next.
  7. In the Project Type page, specify the type of project to create as RTL Project, make sure to uncheck the Do not specify sources at this time option, and click Next.
  8. In the Add Sources page:
    1. Set Target Language to Verilog and Simulator language to Mixed.
    2. Click the Add Files button.
    3. In the Add Source Files dialog box, navigate to the <Extract_Dir>/7_series/src directory for 7 series devices or <Extract_Dir>/UltraScale/src for UltraScale devices.
    4. Select all of the Verilog (.v) source files, and click OK.
    5. In the Add Sources page, change the HDL Source For the testbench.v file to Simulation only.

    6. Verify that the files are added and Copy sources into project is checked. Click Next.
  9. In the Add Constraints (optional) page, click Add Files and select dut_fpga_kc705.xdc in the file browser. In the directory structure, you will find the dut_fpga_kc705.xdc file below the /src folder.

    For UltraScale devices, select dut_fpga_kcu105.xdc in the file browser. In the directory structure, you will find the dut_fpga_kcu105.xdc file below the /src folder.

  10. Click Next to continue.
  11. In the Default Part page, click Boards and select Kintex-7 KC705 Evaluation Platform for 7 series or Kintex UltraScale KCU105 Evaluation Platform for UltraScale devices. Then click Next.
    Tip: When you specify a board, you are also specifying the part you are targeting for your design, in this case an xc7k325tffg900-2 FPGA for 7 series or xcku040-ffva156-2-e FPGA for UltraScale devices.
  12. Review the New Project Summary page. Verify that the data appears as expected, per the steps above, and click Finish.
    Note: It might take a moment for the project to initialize in the Vivado IDE.


  13. In the Settings dialog box (Tools > Settings > Tool Settings > Project), enter the tutorial project directory in the Specify project directory field, so that all reports are saved in the tutorial project directory. Then click OK.

Now, the design is ready for synthesis.