Features - 2.2 English

PG238 MIPI DSI Transmitter Subsystem Product Guide

Document ID
Release Date
2.2 English

1-4 Lane Support

Line rates ranging from:

° 260 to 2500 Mb/s for Versal® ACAPs

° 80 to 2500 Mb/s, refer to the data sheet of your device

Supports different data types with fixed Virtual Channel Identifier (VC) of 0. For list of data types refer to "DSI Data type" GUI parameter

Programmable EoTp generation support

ECC generation for packet header

CRC generation for data bytes (optional)

Optional DCS Command mode support to send command packets long/short

Pixel-to-byte conversion based on data format

AXI4-Lite interface to access core registers

Compliant with AXI4-Stream Video IP and System Design Guide (UG934) [Ref 3] for input video stream

Interrupt generation to indicate subsystem status information

IP Facts Table

Subsystem Specifics

Supported Device Family (1)

Versal ® ACAP, UltraScale+™,

Zynq® UltraScale+ MPSoC,

Zynq ® -7000 SoC, 7 series FPGAs

Supported User Interfaces

AXI4-Lite, AXI4-Stream


Performance and Resource Utilization web page

Provided with Subsystem

Design Files

Encrypted RTL

Example Design

Not Provided (4)

Test Bench

Not Provided

Constraints File


Simulation Model

Not Provided

S/W Driver

Standalone and Linux

Tested Design Flows (3)

Design Entry

Vivado® Design Suite


For supported simulators, see the
Xilinx Design Tools: Release Notes Guide .


Vivado Synthesis


Release Notes and Known Issues

Master Answer Record: 66769

All Vivado IP Changes Logs

Master Vivado IP Changes Logs: 72775

Xilinx Support web page


1. For a complete list of supported devices, see the Vivado IP catalog.

2. Standalone driver details can be found in the Vitis directory (<install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm).

3. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide .

4. MIPI CSI-2 Receiver Subsystem Product Guide (PG232) [Ref 5] uses this IP in example design.