Case 1: Program Timing Values Set and Enable the Core - 2.2 English

PG238 MIPI DSI Transmitter Subsystem Product Guide

Document ID
Release Date
2.2 English

1. Read core_config register to ensure that "control ready" bit is set to '1' before enabling the core any time (for example, after reset or after disabling the core).

2. Select the required settings for Video Mode, EoTp, etc. in the Protocol configuration register.

3. Based on peripheral resolution and timing requirements, arrive the word count values for all the different packets to be sent in video frame (HBP, HFP, HSA, HACT, etc.).

4. Enable the core and send video stream on input interface.

5. The core starts adding the required markers and then consumes the input video stream when the internal timing reaches the active portion of the video.

6. All along this sequence either continuously poll or wait for external interrupt (if enabled) and read Interrupt status register for any errors/status reported.

Figure 3-6: Core Programming Sequence - 1

X-Ref Target - Figure 3-6