The following table shows the revision history for this document.
|
Date |
Version |
Revision |
|---|---|---|
|
04/26/2022 |
2.2 |
Added Register 0x68 to consider D-PHY LP to HS Switching latency. |
|
07/15/2021 |
2.2 |
Editorial update. |
|
07/14/2021 |
2.2 |
• Updated Features section. • Updated Configuration Tab with a new parameter. • Updated Table: Vivado IDE Parameter to User Parameter Relationship with C_EN_CTS_TX parameter. |
|
02/04/2021 |
2.2 |
• Updated Configuration Tab screen for V2.2. • Added information for Line Rate (Mb/s). • Updated Default Line Rate (Mb/s) value for DHY_LINERATE to 800. • Added Versal (VCK190) information in Interoperability. • Updated Licensing and Ordering. • Updated Application Software Development. |
|
07/14/2020 |
2.1 |
Added support for Versal devices. |
|
06/26/2020 |
2.1 |
• New clocking architecture for line rates above 1500 Mb/s, which removes need for ctrl_clk. • Relaxed restriction on input pixels per clock and data types for line rates above 1500 Mb/s. |
|
10/30/2019 |
2.0 |
• Extended line rate support to 2500 Mb/s • Added DCS Long Packet Support |
|
11/14/2018 |
2.0 |
• Added Spartan 7 series support • Updated Unsupported Features section • Added an important note in the Shared Logic Outside the Subsystem section • Updated Simulation section |
|
10/04/2017 |
2.0 |
• MIPI D-PHY serial pins grouped as interface • Board automation support added for FMC:LI-IMX274MIPI-FMC V1.0 which can be placed on ZCU102 FMC HPC0 slot. This FMC can interface MIPI AUO display |
|
04/05/2017 |
1.1 |
• MIPI D-PHY 3.1 changes integrated |
|
10/05/2016 |
1.1 |
• MIPI D-PHY 3.0 changes integrated • 7 Series support • Details on Timing Register(s) calculation procedure and more than 4 Lane implementation added |
|
04/06/2016 |
1.0 |
Initial Xilinx release |