Pin Assignment Tab for UltraScale+ - 2.2 English

PG238 MIPI DSI Transmitter Subsystem Product Guide

Document ID
Release Date
2.2 English

The Pin Assignment tab page allows to select pins. The subsystem pin assignment configuration screen is shown in This Figure .

Note: This tab is not available for 7 series device configurations.

Figure 4-4: Customization Screen - Pin Assignment

X-Ref Target - Figure 4-4


HP IO Bank Selection: Select the HP I/O bank for clock lane and data lane implementation.

Clock Lane: Select the LOC for clock lane. This selection determines the I/O byte group within the selected HP I/O bank.

Data Lane 0/1/2/3: Displays the Data lanes 0, 1, 2, and 3 LOC based on the clock lane selection.