Example Configuration 2 - 2.2 English

Consider an exemplary MIPI DSI Panel with the following specifications:

To generate the values and set timing registers, based on the above example configuration, do the following:

1. HACT(WC) = Active pixels per line * Bits per pixel/8

= 640*8/8

= 640 (decimal) -> 0x280

VACT = Active lines per frame

= 480(decimal) -> 0x1E0

2. Get total line-time in pixel clock.

Pixel Frequency = 50Mhz

Pixel clock period = 1000/50 = 20ns

Total pixel in one line = 640+100 = 740

Total line time = 740*20 = 14800 ns

3. Calculate blanking time.

Byte clock(PPI) frequency = Line-rate/8 = 500/8  = 62.5Mhz

Byte clock period = 1000/62.5 = 16 ns

HACT Duration = Pixels* (Bytes per pixel) * Byte clk Period/ Lanes

= (640 * 1 * 16) /2

= 5120 ns

Blanking time = Line-time - HACT Duration

= 14800 - 5120

= 9680 ns

WC(Bytes) to meet "Blanking time" of 9680 ns

= Blanking time * Lanes / (Byte Period)

= 9680 * 2 / 16

= 1210

4. Get timing parameter based on Video mode

Video mode: Sync Pulses

One line is composed of HSS +HSA + HSE + HBP + HACT + HFP

HSS/HSE -> Short packet -> 4 bytes

HSA/HBP/HACT/HFP -> Long packet -> 4 bytes header + Payload + 2 bytes CRC

Total of 2*4 + 4*6 = 32 bytes are covered in header and footer

Available blanking WC = 1210- 32 = 1178

5. Divide the total available WC across available blanking parameters HSA, HBP and HFP. Considering a ratio of 2:2:2 gives: (The values for HBP and HFP are the distribution of the horizontal blanking words across these parameters. In the examples, Xilinx tries to split these based on a ratio. The MIPI specification does not define the ratio. However, some DSI displays may have specific requirements. Hence, please consult the data sheet for your display.)

Horizontal Sync Active (HSA) = 2*1178/6 = 393

Horizontal Back Porch (HBP) = 2*1178/6 = 393

Horizontal Front Porch (HFP) = 1178 - 393 - 393 =

= 393

6. Set applicable horizontal timing registers with above calculated values.

HSA = 393(decimal) ' 0x189

HBP = 393(decimal) ' 0x189

HFP = 392(decimal) ' 0x188

7. Divide the total available vertical blanking lines between VSA, VBP, and VFP. Considering a ratio of 1:1:1 gives: (The values for VSA, VBP, and VFP are the distribution of the vertical blanking lines across these parameters. In the examples, Xilinx tries to split these based on a ratio. The MIPI specification does not define the ratio. However, some DSI displays may have specific requirements. Hence, please consult the data sheet for your display.)

VSA =  5 (decimal) -> 0x05

VBP =  5 (decimal) -> 0x05

VFP = 5 (decimal) -> 0x05

8. Final consolidate set of horizontal and vertical timing parameters for a DSI panel with 640x480@60 fps, 2-Lane, 500 Mb/s, Compressed data of 8 bit width, Video clock of 50 MHz are as specified below:

HACT = 0x280

HSA = 0x189

HBP = 0x189

HFP = 0x189

VACT= 0x1E0

VSA = 0x05

VBP = 0x05

VFP = 0x05