Consider an exemplary MIPI DSI Panel with the following specifications:
|
Parameter |
Value |
|---|---|
|
MIPI Parameters |
|
|
Line Rate |
1000 Mb/s |
|
Data Type |
RGB888 3 bytes or 24 bits |
|
Video Mode |
Sync Events |
|
Lanes |
4 |
|
Timing Parameters |
|
|
Horizontal Active |
1920 pixels |
|
Horizontal Blanking |
120 pixels |
|
Vertical Active |
1200 lines |
|
Vertical Blanking |
12 lines |
|
Frame Rate |
60 fps |
|
Clock Frequency |
148.5 MHz |
To generate the values and set timing registers, based on the above example configuration, do the following:
1. Get HACT(WC) and VACT
HACT(WC)= Active pixels per line * Bits per pixel/8
= 1920*24/8
= 5760 (decimal) -> 0x1680
VACT = Active lines per frame
= 1200(decimal) -> 0x04B0
2. Get total line-time in pixel clock.
Pixel Frequency = 148.5Mhz
Pixel clock period = 1000/148.5 = 6.73ns
Total pixel in one line = 1920+120 = 2040 (Active Pixels + Blanking Pixels)
Total line time = 2040*6.73 = 13730ns
3. Calculate blanking time.
Byte clock (PPI) frequency = Line-rate/8 = 1000/8 = 125Mhz
Byte clock period = 1000/125 = 8ns
Active pixels per line (HACT) Duration (ns) = Pixels* (Bytes per pixel) * Byte clk Period/ Lanes
= (1920 * 3 * 8) /4
= 11520 ns
Blanking time = Line-time - HACT Duration
= 13730 - 11520
= 2210 ns
Word Count (WC) in Bytes to meet "Blanking time" of 2210 ns
= Blanking time * Lanes / (Byte Period)
= 2210 * 4 / 8
= 1105
4. Get timing parameter based on Video mode.
Video mode: Sync Events
One line is composed of HSS + HBP + HACT + HFP
Horizontal Sync Start (HSS) -> Short packet ->4 bytes
HBP/HACT/HFP -> Long packet -> 4 bytes header + Payload + 2 bytes CRC
Total of 4 + 3*6 = 22 bytes are covered in header and footer.
Available blanking WC = 1105- 22 = 1083
5. Divide the total available WC across available blanking parameters HBP and HFP. Considering a ratio of 5:1 gives: (The values for HBP and HFP are the distribution of horizontal blanking words across these parameters. In the examples, Xilinx tries to split these based on a ratio. The MIPI specification does not define the ratio. However, some DSI displays may have specific requirements. Hence, please consult the data sheet for your display.)
Horizontal Back Porch (HBP) = 902
Horizontal Front Porch (HFP) = 1083 - 902
= 181
6. Set applicable horizontal timing registers with above calculated values.
HBP = 902(decimal) -> 0x386
HFP = 181(decimal) -> 0x0B5
7. Divide the total available vertical blanking lines between VSA, VBP, and VFP.
Considering a ratio of 1:1:1 gives: (The values for VSA, VBP, and VFP are the distribution of the vertical blanking lines across these parameters. In the examples, Xilinx tries to split these based on a ratio. The MIPI specification does not define the ratio. However, some DSI displays may have specific requirements. Hence, please consult the data sheet for your display.)
VSA = 4 (decimal) -> 0x04
VBP = 4 (decimal) -> 0x04
VFP = 4 (decimal) -> 0x04
8. Final consolidate set of horizontal and vertical timing parameters for a DSI panel with 1920x1200 @60 fps, 4-Lane, 1000 Mb/s, RGB888, Video clock of 148.5 MHz are as shown below:
HACT = 0x1680
HBP = 0x386
HFP = 0x0B5
VACT= 0x04B0
VSA = 0x04
VBP = 0x04
VFP = 0x04