Versal ACAP Test Bench

Non-Integer Data Recovery Unit (XAPP1362)

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The TB_HW_VERSAL test bench is available as part of the reference design, and it is designed for the VCK190 demonstration board. This test bench can be implemented to show the NIDRU data recovery capability with both synchronous and asynchronous inputs.

To compile the test benches, source the nidru_design_versal.tcl script from the Vivado Design Suite. The test bench architecture is shown in the following figure.

Figure 1. TB_HW_DRU Test Bench Architecture

The test bench includes:

  • A 25G receiver, based on the NIDRU, operating on a 156.25 MHz reference clock.

    The TX channel transmits data synchronized with REFCLK 200 MHz. The channels are connected via a SFP cable so that the receiver receives data at a frequency not synchronized to its own reference clock.

    The two reference clocks are generated on board by using the system controller. The reference clock frequencies are configured through the serial interface on the VCK190 board.

  • TX side

    A PRBS generator continuously sending a PRBS 7 or PRBS 31 pattern. Each of the two PRBS generators can be forced to generate an error using the Vivado Logic Analyzer to show error detection on the corresponding PRBS checker.

  • RX side

    A PRBS checker continuously checking the incoming PRBS 7 or PRBS 31 pattern. The ERR output indicates detection of at least one error from the last ERR_RST. ERR is connected to the virtual input/output (VIO) and checked in real time. An error counter is also provided.

The specific PRBS pattern used in this application note for both the generator and the checker is based on the polynomial x31+x28+ 1 for PRBS 31, x7+x6+ 1 for PRBS 7 and can be changed to any other industry standard PRBS type.

Each PRBS checker works on the data delivered by the barrel shifter, which is instantiated right after each NIDRU block. The following figure reports the detailed description of all signals of the test bench that are controlled by the Vivado Logic Analyzer. The pin names are consistent across the VHDL code, the logic analyzer project, and this application note.

Figure 2. Vivado Logic Analyzer Controlling the Demonstration Test Bench

The transmitter can be set to generate a PRBS pattern, as described previously. When the application works properly, all LEDs are green. In case of an error in the datapath, the corresponding LED (highlighted with dashes in the previous figure) for the chk_okko_gt0 signals is red. The example design needs two asynchronous and independent clocks. For the receiver, the frequency is 156.25 MHz. The clock for the transmitter can be a different frequency accordingly to the selected data rate.

The VCK190 board provides the required clocks through the system controller. In the example design supplied with this application note, the system controller can be programmed by the system controller user interface and using the serial interface on the VCK190 board. The system controller GUI software can be downloaded from the VCK190 lounge page. The following figure shows the settings for generating the correct frequency of 156.25 MHz.

Figure 3. Clock Setup for Receiver