Download the reference design files for this application note from the Xilinx website.
Reference Design Matrix
The following checklist indicates the procedures used for the provided reference design.
| Parameter | Description |
|---|---|
| General | |
| Developer name | Xilinx |
| Target devices | Versal ACAP |
| Source code provided? | Yes, partially encrypted |
| Source code format (if provided) | VHDL |
| Design uses code or IP from existing reference design, application note, 3rd party or Vivado software? If yes, list. | This reference design uses code from An Attribute-Programmable PRBS Generator and Checker (XAPP884). |
| Simulation | |
| Functional simulation performed | Yes |
| Timing simulation performed? | No |
| Test bench provided for functional and timing simulation? | Yes |
| Test bench format | VHDL |
| Simulator software and version | Mentor Graphics Questa Advanced Simulator 10.4c |
| SPICE/IBIS simulations | No |
| Implementation | |
| Synthesis software tools/versions used | Vivado synthesis 2020.2 |
| Implementation software tool(s) and version | Vivado implementation 2020.2 |
| Static timing analysis performed? | Yes |
| Hardware Verification | |
| Hardware verified? | Yes |
| Platform used for verification | VCK190 evaluation board |