Resources - XAPP1362

The NIDRU is designed with efficient structures only (adders, multipliers, accumulators, and shifters). The resource requirements for the Versal adaptive SoC are summarized in the following table.

Table 1. Hardware Resources Required for the NIDRU in Versal Adaptive SoCs
Synthesis Type (NIDRU_DATA_WIDTH)	Eye Scan (PH_NUM)	Flip-Flops	LUTs	BUFG
32	0	1191	2308	1
	1	2483	4143
	2	3105	5072
64	0	2336	4653	1
	1	5048	9148
	2	6380	11451
128	0	4481	9378	1
	1	9575	18488
	2	12098	23055
Only one BUFG is required even if many channels are being set up, and even if all are working at different data rates. These results were obtained using the Vivado Design Suite, version 2024.1. The strategy used for the synthesis and implementation was Default and the CLK period was 6.4 ns.