Simulating the NIDRU

Non-Integer Data Recovery Unit (XAPP1362)

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1.0 English

The purpose of the TB_SIM_DRU_JITTER test bench is to simulate the ability of the NIDRU to operate at several popular data rates (see the following table) with synchronous and plesiochronous serial inputs. The simulation covers the nine cases shown in the following table in sequence. Any data rate can be added as an additional case. The cases show the ability of the NIDRU to operate at both fractional and integer oversampling rates.

Table 1. Simulation Cases
Protocol (Case #) Data Rate Ref Clock (Oversampling Rate) Oversampling Rate Minimum Width Supported
Proprietary (1) 250 Mbit/s 125 MHz 10 20
OC3 (2) 155.52 Mbit/s 125 MHz 16.075 4
SDI (3) 270 Mbit/s (+100 ppm) 148.5 MHz 11 20
OC3 (4) 155.52 Mbit/s 155.52 MHz 20 4
OC12 (5) 622.08 Mbit/s 125 MHz 4.019 20
FE (6) 125 Mbit/s 155.52 MHz 24.8832 4
Proprietary (7) 8 Gbit/s 229 MHz 3.664 128
Proprietary (8) 4 Gbit/s 229 MHz 7.328 64
Proprietary (9) 10 Gbit/s 229 MHz 2.9312 128

To run the simulation script:

  1. Open a DOS command window.
  2. Change to the /scripts directory.
  3. Open the Mentor Graphics Questa Advanced Simulator.
  4. In the simulator, run the run_sim_do script.

Although the test bench has been designed for the Questa Advanced Simulator only, the NIDRU core is expected to operate with the following broader set of simulation tools.

  • Vivado┬« Simulator
  • ModelSim
  • Synopsys VCS

The architecture implemented in the tb_sim_nidru_v_3_0.vhd test bench is shown in the following figure. An ideal deserializer and serializer are used instead of a full transceiver to minimize the simulation time. The serializer and deserializer datapath is 4, 20, 32, 64, or 128, programmable through the DTIN_WIDTH attribute.

Figure 1. TB_SIM_NIDRU Block Diagram

The test bench contains two clock domains:

  • The clock domain of the line, synchronized to CLK_DT.
  • The clock domain of the DRU, synchronized to REFCLK and to HF_CLK.

The pseudo-random binary sequence (PRBS) generator works at full speed on CLK_DT and can generate any kind of industry standard PRBS (see An Attribute-Programmable PRBS Generator and Checker (XAPP884)). The ideal deserializer, the NIDRU, and the PRBS checker all work on the local REFCLK domain, a divided version of HF_CLK.

During test case 1, a 1 ns phase step datastream is applied to the input (see the following figure). The purpose of this is to show the ability of the NIDRU to respond with an exponential locking process to an input phase step and to prove the stability of the loop.

Figure 2. NIDRU Response Following a 1 ns Step In the Input Phase

During test case 2 and 5, the eye scan is plotted with PH_NUM=1 (see the following figure). The eye is scanned with one single phase from left to right.

Figure 3. Eye Scan with PH_NUM=1 (Simulation)

An example of an eye scan with 2 phases (PH_NUM=2) is shown in the following figure. The left and right half of the eye are scanned at the same time.

Figure 4. Eye Scan with PH_NUM=2 (Simulation)