Use Debug Cores to Monitor Activity

Fast Partial Reconfiguration Over PCI Express (XAPP1338)

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While the device is undergoing partial reconfiguration, the data stream can be monitored to confirm bitstream formatting is correct. Multiple ILA debug cores have been inserted into this sample design, but the most straightforward one to use sits in the top level alongside the ICAP primitive.
  1. Open the Vivado® Design Suite hardware manager feature, and connect to the target board.
  2. To see the debug cores, refresh the device.
  3. In one of the ILA core windows, click Specify the probes file links to find Bitstreams/ design_1_wrapper_shift_right.ltx.
  4. In hw_ila_3, click + to add probes in the Trigger Setup window.
  5. Select M_AXIS_0_tdata[31:0], and click OK.
  6. For Radix, select [H] (hexadecimal).
  7. For Value, set 5599_AA66 to watch for the bitstream sync word. This is the bit-swapped version that the ICAP expects to set the configuration engine to programming mode.

  8. Arm the trigger, and then partially reconfigure the device (as described in the previous section). Data should be captured as soon as the partial bitstream is sent.
  9. In the captured data, you will see the beginning of the bitstream delivery, not long after tvalid has risen high.

The AXI4 bus can be monitored for its activity by using the ILA core instances hw_ila_1 and hw_ila_2. These cores can be found within the block diagram. They monitor the output of:

  • XDMA (system_ila_0)
  • data_fifo (system_ila_1)