Fast Partial Reconfiguration Over PCI Express (XAPP1338)

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UltraScale™ and UltraScale+™ devices support Partial Reconfiguration (PR), which is the ability to dynamically change the configuration of a portion of the device, while the rest of the device continues to operate normally. Most configuration ports are permitted for delivery of partial bitstreams, so users have a great deal of flexibility as they build their system requirements. For systems based on PCI Express® ( PCIe® ), users can use this established connection to store and deliver partial bitstreams.

One Endpoint per device has a dedicated connection to the FPGA’s configuration engine via the MCAP. This connection uses resources efficiently, but the bandwidth of PCIe data partial bitstream delivery through the MCAP is limited to one DWORD configuration writes, which can give a bandwidth of 3-6 MB/s in typical systems. Most systems only send one configuration at a time, and because configuration writes are non-posted, a second configuration write will not be sent until the completion from the preceding write is received. These restrictions lead to very low PCIe bandwidth compared to what is achievable with the PCIe protocol.

The fastest possible interface to the configuration engine for PCIe systems is through the internal configuration access port (ICAP). This SelectMAP-style interface can support 32-bit wide bitstream data at 200 MHz (800 MB/s) for monolithic devices and 125MHz (500 MB/s) for devices using stacked silicon interconnect (SSI) technology. This application note shows a basic design that connects a PCIe direct memory access (DMA) IP to the ICAP, providing the maximum throughput, allowing users to partially reconfigure as fast as the silicon allows.