Reference Design Matrix

Fast Partial Reconfiguration Over PCI Express (XAPP1338)

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Table 1. Reference Design Matrix. The following checklist indicates the procedures used for the provided reference design.
Parameter Description
Developer name Xilinx
Target devices
  • XCVU9P-FLGA2104-2L
  • XCKU5P-FFVB676-2
Source code provided? N
Source code format (if provided) N/A
Design uses code or IP from existing reference design, application note, third-party, or Vivado software? If yes, list. N
Functional simulation performed N
Timing simulation performed? N
Test bench provided for functional and timing simulation? N
Test bench format N/A
Simulator software and version N/A
SPICE/IBIS simulations N
Synthesis software tools/versions used Vivado synthesis feature
Implementation software tool(s) and version Vivado implementation feature
Static timing analysis performed? N
Hardware Verification
Hardware verified? Y
Platforms used for verification
  • VCU118
  • KCU116