Experiments

Continuing Experiments of Atmospheric Neutron Effects on Deep Submicron Integrated Circuits (WP286)
Document ID
WP286
Release Date
2023-04-12
Revision
2.1 English

Each Rosetta experiment consisted of multiple sets of 100 of the largest available AMD FPGAs using differing technologies, located at different altitudes. All tested components were fabricated by AMD foundry partners, using their planar or FinFET technologies.

The following table lists the locations of the experiments. Table 2 and Table 3 list the device type, technology, and quantity.

Table 1. Locations of AMD Rosetta Experiments
Location Altitude (Feet) Adjusted Altitude Factor 1
Lead, SD –5800 2 0.00
Rustrel, France –1600 2 0.00
San Jose, CA 257 0.75
Marseilles, France 359 1.08
Longmont, CO 4958 4.11
Albuquerque, NM 5145 3.34
Pic du Bure, France 8196 6.00
Pic du Midi, France 9298 8.62
Leadville, CO 10200 12.22
Echo Lake, CO 10600 13.02
Aiguille du Midi, France 11289 12.45
White Mountain, CA 12442 19.48
Mauna Kea, HI 13000 11.35
  1. Adjustments have been made for the influence of minimum solar sunspots on cosmic ray flux.
  2. Underground facilities.
Table 2. Devices Previously Tested (WP286 v1.x)
Device Family Device Number Technology Quantity
Kintex™ 7 FPGAs XC7K325T 28 nm 300
Virtex™ 7 FPGAs XC6VLX240T 40 nm 300
Spartan™ 6 FPGAs XC6SLX150 45 nm 200
Virtex 4 FPGAs XC4VLX25 90 nm 400
Virtex 4 FPGAs XC4VLX60 90 nm 300
Spartan 3 FPGAs XC3S1500 90 nm 200
Virtex-II FPGAs XC2V6000 150 nm 300
Virtex-II Pro FPGAs XC2VP50 130 nm 600
Table 3. Devices Presently Under Test (WP286 v2.x)
Device Family Device Number Technology Quantity
Kintex UltraScale™ FPGAs XCKU040 20 nm 400
Kintex UltraScale+™ FPGAs XCKU9P 16 nm 400
Versal™ devices VC1902 7 nm 300

Over the years, the Rosetta program has changed to include prediction of error rates using TCAD modeling, fabrication and beam testing of test devices, beam testing of production devices, and testing using the atmospheric placement of arrays, as well as underground arrays.

In the IC design of the AMD FPGAs, the individual memory cells (implemented as static latches) used for configuration, look-up tables, and block RAM were all simulated for their sensitivity to single event upsets.

To detect alpha contamination in packaging and assembly, the experimental groups were rotated through the three altitudes in addition to using the underground facility. Any evidence of a constant upset rate due to alpha particles would be observed as a non-altitude, non-latitude dependent factor in the resulting upsets, or measured directly underground.