All atmospheric and alpha information is present in the Device Reliability Report (UG116), which AMD updates twice per year. The report summarizes the atmospheric and beam test results for all FPGA device technologies. The error rate is stated either in failures in time (FIT) per billion hours or in mean time between events in hours, days, or years. A functional failure of the user data due to the single event upset rate then becomes mean time between functional failure in hours, days, or years. Estimation of Single Event Upset Probability Impact of FPGA Designs [Ref 4] describes the relationship between the mean time between failure (MTBF) configuration bit and mean time between functional failure, which is based in estimating the Device Vulnerability Factor (DVF). Not every upset results in a functional failure because upsets can be masked in either time or space by a user’s design. The DVF factor has been shown to be commonly from 2%, to no more than 10%, in actual device beam testing. A reasonable DVF estimate when the design is not known is 5%.
Since on average, it takes from 10 to 50 upsets to actually cause a functional failure, determining the field failure rate of any design needs to be appropriately derated. The recommended worst-case estimate is to use a factor of ten (10) as the derating factor.
An essential bits feature of the AMD bitstream generation tools provides a design-specific estimate of the derating for any design. In addition to the Device Reliability Report, AMD also provides a pre-design failures-in-time (FIT) estimator that helps customers determine if SEU mitigation is needed, given their design specifications.