This section describes how to apply the AXI Register Slice IP to pipeline the AXI pathways crossing between two SLR regions when targeting an SSI FPGA.
Assume two IP cores (A and B) with an AXI Memory-Mapped point-to-point connection that is known to cross from one SLR to another:
Figure 1. AXI Memory-Mapped Connections Across SLRs in SSI Devices
To facilitate timing closure of those AXI Memory-Mapped interfaces, crossing the SLRs with flop-to-flop paths is helpful. This can be accomplished, in one of two methods, by using the Vivado IP integrator design entry.