Implemented as a two-deep FIFO buffer, this mode supports throttling by the channel source and/or channel destination as well as back-to-back transfers without incurring bubble cycles (up to 100% duty cycle). This mode is appropriate on W and R channels carrying bandwidth-critical AXI4 or AXI3 burst transfers.
This mode is selected as "Full" in the configuration dialog. Fully-registered mode drives registered payload outputs and registered VALID and READY handshake outputs as shown in the figure.
Figure 1. Fully-Registered AXI Register Slice Diagram
The figure shows that the Fully-Registered mode introduces one latency cycle, but no bubble cycles.
Figure 2. Fully-Registered Mode Timing Diagram
