The S_AXI and M_AXI interfaces are both synchronized by the aclk input. The
AXI Register Slice IP does not perform clock conversion.
When SLR TDM Crossing mode is selected for any AXI channel, the core also enables its ACLK2X input and requires that it be driven by a clock produced by the same source as ACLK with exactly 2x the ACLK frequency and zero-phase (edge-aligned).