- Individually configurable for each of the five AXI channels.
- Facilitates timing closure by trading-off frequency versus latency.
- One latency cycle per register-slice by default.
- Able to propagate AXI traffic with no loss in data throughput (without bubble cycles) under all AXI handshake conditions.
- Optional pipelining to cross super logic region (SLR) in stacked silicon interconnect (SSI) devices. See Large FPGA Methodology Guide: Including Stacked Silicon Interconnect (SSI) Technology (UG872) for more information.