The following table lists the Master Interface signals for the core.
| Signal Name | I/O | Default | Width | Description (Range) |
|---|---|---|---|---|
| m_axi_awid | O | ID_WIDTH | Write Address Channel Transaction ID | |
| m_axi_awaddr | O | ADDR_WIDTH | Write Address Channel Address | |
| m_axi_awlen | O |
AXI4: 8 AXI3: 4 |
Write Address Channel Burst Length Code (0–255) | |
| m_axi_awsize | O | 3 | Write Address Channel Transfer Size Code (0–7) | |
| m_axi_awburst | O | 2 | Write Address Channel Burst Type (0–2) | |
| m_axi_awlock | O |
AXI4: 1 AXI3: 2 |
Write Address Channel Atomic Access Type (0, 1) | |
| m_axi_awcache | O | 4 | Write Address Channel Cache Characteristics | |
| m_axi_awprot | O | 3 | Write Address Channel Protection Bits | |
| m_axi_awregion | O | 4 | AXI4 Write Address Channel Address Region Index | |
| m_axi_awqos | O | 4 | Write Address Channel Quality of Service | |
| m_axi_awuser | O | AWUSER_WIDTH | User-defined AW Channel Signals | |
| m_axi_awvalid | O | 1 | Write Address Channel Valid | |
| m_axi_awready | I | REQ | 1 | Write Address Channel Ready |
| m_axi_wid | O | ID_WIDTH | Write Data Channel Transaction ID for AXI3 Slaves | |
| m_axi_wdata | O | Data Width Converter: M_AXI_DATA_WIDTH; Others: DATA_WIDTH |
Write Data Channel Data | |
| m_axi_wstrb | O | Data Width Converter: M_AXI_DATA_WIDTH/8; Others: DATA_WIDTH/8 |
Write Data Channel Data Byte Strobes | |
| m_axi_wlast | O | 1 | Write Data Channel Last Data Beat | |
| m_axi_wuser | O | WUSER_WIDTH | User-defined W Channel Signals | |
| m_axi_wvalid | O | 1 | Write Data Channel Valid | |
| m_axi_wready | I | REQ | 1 | Write Data Channel Ready |
| m_axi_bid | I |
AXI3, AXI4: REQ AXI4-Lite: d/c |
ID_WIDTH | Write Response Channel Transaction ID. |
| m_axi_bresp | I | 0b00 | 2 | Write Response Channel Response Code (0–3) |
| m_axi_buser | I |
AXI3, AXI4: 0 AXI4-Lite: d/c |
BUSER_WIDTH | User-defined B Channel Signals |
| m_axi_bvalid | I | REQ | 1 | Write Response Channel Valid |
| m_axi_bready | O | 1 | Write Response Channel Ready | |
| m_axi_arid | O | ID_WIDTH | Read Address Channel Transaction ID | |
| m_axi_araddr | O | ADDR_WIDTH | Read Address Channel Address | |
| m_axi_arlen | O |
AXI4: 8 AXI3: 4 |
Read Address Channel Burst Length Code (0–255) | |
| m_axi_arsize | O | 3 | Read Address Channel Transfer Size Code (0–7) | |
| m_axi_arburst | O | 2 | Read Address Channel Burst Type (0–2) | |
| m_axi_arlock | O |
AXI4: 1 AXI3: 2 |
Read Address Channel Atomic Access Type (0,1) | |
| m_axi_arcache | O | 4 | Read Address Channel Cache Characteristics | |
| m_axi_arprot | O | 3 | Read Address Channel Protection Bits. | |
| m_axi_arregion | O | 4 | AXI4 Read Address Channel Address Region Index | |
| m_axi_arqos | O | 4 | AXI4 Read Address Channel Quality of Service | |
| m_axi_aruser | O | ARUSER_WIDTH | User-defined AR Channel Signals | |
| m_axi_arvalid | O | 1 | Read Address Channel Valid | |
| m_axi_arready | I | REQ | 1 | Read Address Channel Ready |
| m_axi_rid | I |
AXI3, AXI4: REQ AXI4-Lite: d/c |
ID_WIDTH | Read Data Channel Transaction ID |
| m_axi_rdata | I | REQ | Data Width Converter: M_AXI_DATA_WIDTH; Others: DATA_WIDTH |
Read Data Channel Data |
| m_axi_rresp | I | 0b00 | 2 | Read Data Channel Response Code (0–3) |
| m_axi_rlast | I |
AXI3, AXI4: REQ AXI4-Lite: d/c |
1 | Read Data Channel Last Data Beat |
| m_axi_ruser | I |
AXI3, AXI4: 0 AXI4-Lite: d/c |
RUSER_WIDTH | User-defined R Channel Signals |
| m_axi_rvalid | I | REQ | 1 | Read Data Channel Valid |
| m_axi_rready | O | 1 | Read Data Channel Ready |