| Port Name | I/O | Description |
|---|---|---|
| aclk | I | Input clock at which all the interfaces of this block are synced and working |
| aresetn | I | Input reset for this block, at which all the things inside would be reset |
| S_AXI | I | Input interface that is used for the host side to drive the transactions or data from or to the host |
| Sxx_AXIS | I | Slave AXIS input to take the read data from the debug cores, such as AXIS_ILA or VIO |
| Mxx_AXIS | O | Master AXIS output to give the write data to the debug cores, such as AXIS_ILA or VIO |
| S_BSCAN | I | Optional input interface, used on the host side to drive the transactions or data to or from the host |
Note: The Sxx_AXIS and
Mxx_AXIS in the table above shows the S_AXIS and M_AXIS interfaces from the IP. The
subscript XX denotes the number of such interfaces that would appear in the design,
according to the configuration you have set. For example, if you have selected the number of
debug cores as 3, then only S00_AXIS and M00_AXIS, S01_AXIS and M01_AXIS, S02_AXIS and
M02_AXIS would appear in the IP.
For detailed information of the signals in the AXI as well as AXI4-Stream interfaces, refer to the AXI protocol specification document mentioned in Vivado Design Suite: AXI Reference Guide (UG1037).