Features - 2.0 English

AXI4 Debug Hub LogiCORE IP Product Guide (PG361)

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2.0 English
  • User-selectable number of debug cores. The maximum number of cores which can be connected are 64.
  • For the connection from the host side, the AXI interface is configurable according to the Master AXI parameters.
  • Provides a communication path using JTAG or HSDP debug interface between an AMD Hardware Manager software and debug cores such as ILA, VIO.
  • Support for up to 64 debug cores attached to the Debug Hub AXI ports. The number of cores are user selectable.
  • Parameterizable AXI ports for connectivity to Network-on-Chip and other AXI master interfaces.
  • Optional BSCAN interface to provide a fallback path for debugging the designs, even in hung situation of AXI path.