Core Overview - 2.0 English

AXI4 Debug Hub LogiCORE IP Product Guide (PG361)

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2.0 English

The Debug Hub provides an interface between AMD Vivado™ Hardware Manager tool and up to 64 debug cores (such as ILA and VIO) via JTAG or HSDP debug interfaces of the target AMD Versal™ device.

The Debug Hub IP provides AXIS interface for connectivity to debug cores while an AXI interface attaches it to Network-on-Chip or other type of AXI master interfaces.

Figure 1. Debug Hub