Core Overview - 2.0 English - PG361

AXI4 Debug Hub LogiCORE IP Product Guide (PG361)

Document ID
PG361
Release Date
2024-11-13
Version
2.0 English

The Debug Hub provides an interface between AMD Vivado™ Hardware Manager tool and up to 64 debug cores (such as ILA and VIO) through JTAG or HSDP debug interfaces of the target AMD Versal™ device.

The Debug Hub IP provides AXIS interface for connectivity to debug cores while an AXI interface attaches it to a Network-on-Chip or other type of AXI master interface.

Figure 1. Debug Hub