|
Core Specifics |
| Supported Device Family
1
|
AMD Versal™
Adaptive
SoC |
| Supported User Interfaces |
IEEE Standard 1149.1 – JTAG |
| Provided with
Core
|
| Design Files |
RTL |
| Example Design |
Verilog |
| Test Bench |
Not Provided |
| Constraints File |
Xilinx Design Constraints (XDC) |
| Simulation Model |
Not Provided |
| Supported S/W Driver |
N/A |
| Tested Design Flows
2
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
Not Provided |
| Synthesis |
Vivado Synthesis |
| Support |
| All Vivado IP Change
Logs |
Master Vivado IP Change
Logs: 72775
|
|
Support web
page
|
- For a complete list of supported devices, see the AMD Vivado™
IP catalog.
- For the supported versions of the tools, see
the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|