Clocking - 1.2 English

Integrated Logic Analyzer (ILA) with AXI4-Stream Interface LogiCORE IP Product Guide (PG357)

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1.2 English

The clk input port is the clock used by the ILA core to register the probe values. For best results, it should be the same clock signal that is synchronous to the design logic that is attached to the probe ports of the ILA core. When connecting manually with AXI Debug Hub, the aclk signal should be synchronous to AXI Debug Hub clock input port.