Core Overview - 1.2 English

Integrated Logic Analyzer (ILA) with AXI4-Stream Interface LogiCORE IP Product Guide (PG357)

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1.2 English

Signals and interfaces in the FPGA design are connected to an ILA probe and slot inputs. These signals and interfaces, attached to the probe and slot inputs respectively, are sampled at design speeds and stored using on-chip block RAM. Signals and interfaces in the AMD Versal™ adaptive SoC design are connected to ILA probe and slot inputs. These attached signals and interfaces are sampled at design speeds using the core clock input and stored in on-chip block RAM memories. The core parameters specify the following:

  • Number of probes (up to 1024) and probe width (1 to 1024).
  • Number of slots and interface options.
  • Trace sample depth.
  • Data and/or trigger property for probes.
  • Number of comparators for each probe.

Communication with the ILA core is conducted using an instance of the AXI Debug Hub that connects to the Control, Interface, and Processing System (CIPS) IP core.

Figure 1. ILA Core

After the design is loaded into the Versal adaptive SoC, use the AMD Vivado™ logic analyzer software to set up a trigger event for the ILA measurement. After the trigger occurs, the sample buffer is filled and uploaded into the Vivado logic analyzer. You can view this data using the waveform window.

The probe sample and trigger functionality is implemented in the programmable logic region. On-chip block RAM or UltraRAM memory based on the storage target you have selected during customization which stores the data until it is uploaded by the software. No user input or output is required to trigger events, capture data, or to communicate with the ILA core. ILA core is capable of monitoring interface level signals, it can convey transaction level information such as the outstanding transactions for AXI4 interfaces.