The Control Interfaces and Processing System IP core is also used to configure the PL interfaces to the XRAM integrated block on devices that support it.
Figure 1. Configuring the PL AXI Interfaces to XRAM in the CIPS IP
Note: In some devices having accelerator RAM (XRAM)
option (for example; VE2002), the PL is not accessible from XRAM.
Note: For more information on XRAM, see the XRAM and
DDRMC related sections in
Versal
Adaptive SoC Technical Reference Manual (AM011).