High-Speed Debug Port is a protocol that provides debug and trace for the programmable logic (PL), processing system (PS), and the AI Engines. HSDP can use gigabit transceivers on the device to provide better performance than the JTAG interface.
As HSDP is a protocol, the transaction layer is handled by the debug packet controller (DPC) and the link layer can be one of the four interfaces listed below:
- JTAG
- Select JTAG as the pathway to/from Debug Packet Controller.
- HSDP Aurora (hardened Aurora IP)
- Select Aurora as the pathway to/from Debug Packet Controller. The allowed range for GT Refclk Freq for HSDP Aurora is 60-820 MHz.
- CPM PCIe Controller
- Select PCIe as the pathway to/from debug packet controller.
- PL Aurora (soft Aurora IP)
- Select PL as the pathway to/from the debug packet controller.
Warning: Be very careful
when using the hardened HSDP Aurora as this can impose limitations on the GTY
transceivers available to the rest of the design. For more information on the
limitations, see XPIPE GTY Transceiver Channels table in
Versal
Adaptive SoC Technical Reference Manual (AM011). For more information on
high-speed debug port see Integrated Debug chapter in
Versal
Adaptive SoC Technical Reference Manual (AM011).
Warning: The
refclk interface name is associated with the HSDP interface and not with
the physical refclock (0/1) on the device. For example; gt_refclk1 corresponds to HSDP1. Similarly, gt_refclk0 corresponds to HSDP0 and not to reference clock selection. Figure 1. High Speed Debug Port
