Clock configuration for the HSM0, which is the source for the AIE PLL and
HSM1, which is source for the DDR PLL. HSM0 and HSM1 connectivity is dedicated
and not shown in the IP integrator canvas.Note: In multi-SLR devices, the AIE might be located in a
secondary SLR. For instance, in the VP2802 device, there are four SLRs. The
AIE is positioned in SLR3, with SLR3 HSM0 serving as the source for the AIE
PLL. SLR0 HSM0 is not used. Refer to the datasheet to determine which SLR
the AI Engine is
located on.