Revision History - 3.4 English

The following table shows the revision history for this document.

Section	Revision Summary
05/30/2024 Version 3.4
CIPS Interactive Block Diagram	Updated section.
High-Speed Debug Port (HSDP)	Updated section.
Tamper Events/Response Configuration	Updated section.
PS-NoC Interfaces	Updated section.
10/18/2023 Version 3.4
CIPS Interactive Block Diagram	Added new section.
Design Flow Steps	Updated all figures.
PS-NoC Interfaces	Updated section.
NoC Interfaces	Updated section.
SD Configuration	Added a table.
Upgrading	Added a note.
05/16/2023 Version 3.3
Design Flow Steps	Updated figures for CIPS v3.3.
Device Integrity	Updated for new tamper and clock monitor features.
AXI4 I/O Compliant Interfaces	Added a link to AR76566.
PS-NoC Interfaces	Updated PS-NoC Interfaces section for new HSM1 clock port.
05/11/2022 Version 3.2
Design Flow Steps	Added SD Configuration section. Updated screens from CIPS 3.2. Updated XilSEM Library Configuration, Block Automation, System Monitor, and Boot Mode sections.
10/27/2021 Version 3.1
Design Flow Steps	Updated screens for CIPS 3.1.
Output Clocks	Added LPD Top switch clocking restriction.
AXI4 I/O Compliant Interfaces	Added ACE-Lite GUI information.
Boot Mode	Added `CONFIG.PS_PMC_CONFIG` parameter. Deleted `CONFIG.PS_USE_STARTUP` parameter.
Upgrading	Added appendix.
06/16/2021 Version 3.0
Design Flow Steps	Updated screens from CIPS 3.0. Added Choosing a Design Flow, CIPS Presets, and Power Configuration sections. Added support of CPM5.
Automation	Modified Board automation through Block automation. Added support of LPDDR in Block Automation.
Tamper Events/Response Configuration	Deleted Voltage Tamper event.
XilSEM Library Configuration	Modified content for detect and correct soft errors.
12/04/2020 Version 2.1
Initial release.	N/A